This invention relates to synchronizing circuits; and more particularly, it relates to synchronizers which sample an asynchronous digital input signal with a clock and operate with low error rates.
Synchronizers, of the type with which the present invention is concerned, have use whenever digital information is to be transferred between two digital modules that operate asynchronously to one another. For example, digital computers usually have their own internal clock to which their internal operations are synchronized; and thus, when one computer sends information to a second computer, the information will arrive at the second computer asynchronously with respect to its internal clock. Similarly, when information is entered by an operator via a keyboard into a computer, the keys are pressed asynchronously with respect to the computer's internal clock.
In the above cases, a synchronizer circuit is often used to sample and hold the incoming data until it can be received by the receiving computer. However, since the incoming data is asynchronous, there is a certain probability that the data will change at the same time that it is being sampled. And, when that happens, the sample that is taken may be at an intermediate voltage level which lies between a full "1" and a full "0".
Then, if the intermediate voltage is operated on by the receiving computer, an error can occur. This is because the intermediate voltage can be interpreted by the computer as a "1" when it actually was a "0", and vice versa. Consequently, it is important that the synchronizer circuit be designed to reduce the probability with which such intermediate voltage errors occur.
One synchronizer circuit of the prior art which is related to the present invention is described in U.S. Pat. No. 3,953,744 which issued in 1976 to Kawagoe. However, with the '744 synchronizer, the probability of an intermediate voltage error occurring is too high; and this will be explained in detail in the Detailed Description in conjunction with FIG. 10.
Accordingly, it is a primary object of the invention to provide an improved synchronizing circuit which greatly reduces intermediate voltage errors.